1. Field of Invention
The present invention relates to a method for manufacturing a dielectric layer. More particularly, the present invention relates to a method for manufacturing a dielectric layer with a relatively low dielectric constant in a dual-damascene interconnect structure.
2. Description of Related Art
In the process for manufacturing an ultra large-scale integrated circuit, over one hundred thousand of transistors are located a silicon substrate with an area of about 1-2 square centimeters. Additionally, in order to increase the integration of the integrated circuits (ICs), the density of wires used to electrically couple the transistors to each other or the other devices to each other is increased. Therefore, in accord with the increased interconnect manufacturing requirements of miniaturized MOS transistors, it is increasingly necessary for IC manufacturing to adopt a design with more than two metal layers. Taking a logic circuit as an example, there are six metal layers in the current integrated circuit.
However, due to the increasingly high integration of ICs, the distance between the adjacent wires is decreased. If the dielectric constant of the IMD layer used as an electrically isolated material between the wires cannot be effectively decreased, unnecessary capacitive and inductive coupling between the adjacent conductive wires occurs. Hence, the RC time delay is increased caused by the capacitive and inductive coupling between the adjacent conductive wires. Moreover, the rate of data transmission between the devices is decreased due to the increasing of the RC time delay. Hence, the ability of the devices is limited.
Typically, in the dual damascene process, the inter-metal dielectric layer and the intra-metal dielectric layer are made of a dielectric material with a relatively low dielectric constant, such as fluorosilicate glass (FSG), to decrease the RC time delay between the metal layers and between the wires. However, the dielectric constant of fluorosilicate glass is about 3.5, only 15% lower than that of oxide (k=4.1), so that the reduction of RC time delay is limited. Furthermore, in the requirement for the dielectric layer with a dielectric constant lower than 3, the other dielectric material with a low dielectric constant including organic and inorganic dielectric material are still not mature for production. Therefore, organic dielectric material and inorganic dielectric material are seldom used in the integrated circuit.